Mer/Status/SmartQ5

Mer is back : Please visit http://www.merproject.org to learn more about this news.

For general SmartQ tips, see tips for SmartQ.

Notes on SmartQ 5 MID:

rootfs is on mmcblk0 (1G) p1 (rootfs, homefs, swap) booted by uboot

Processor	: ARMv6-compatible processor rev 6 (v6l)
BogoMIPS	: 99.78
Features	: swp half thumb fastmult vfp edsp java 
CPU implementer	: 0x41
CPU architecture: 7
CPU variant	: 0x0
CPU part	: 0xb76
CPU revision	: 6
Cache type	: write-back
Cache clean	: cp15 c7 ops
Cache lockdown	: format C
Cache format	: Harvard
I size		: 16384
I assoc		: 4
I line length	: 32
I sets		: 128
D size		: 16384
D assoc		: 4
D line length	: 32
D sets		: 128

Hardware	: SMDK6410
Revision	: 0000
Serial		: 0000000000000000

Linux version 2.6.24.7 (root@gqwang2007-desktop) (gcc version 4.3.2 (Sourcery G++ Lite 2008q3-72) ) #2725 PREEMPT Fri Apr 10 11:46:59 CST 2009
CPU: ARMv6-compatible processor [410fb766] revision 6 (ARMv7), cr=00c5387f
Machine: SMDK6410
Ignoring unrecognised tag 0x00000000
Memory policy: ECC disabled, Data cache writeback
On node 0 totalpages: 29184
  DMA zone: 228 pages used for memmap
  DMA zone: 0 pages reserved
  DMA zone: 28956 pages, LIFO batch:7
  Normal zone: 0 pages used for memmap
  Movable zone: 0 pages used for memmap
CPU S3C6410 (id 0x36410101)
S3C6410: core 532.000 MHz, memory 133.000 MHz, peripheral 66.500 MHz
S3C6410: EPLL 192.000 MHz
S3C64XX Clocks, (c) 2007 Samssung Electronics
CPU0: D VIPT write-back cache
CPU0: I cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets
CPU0: D cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 28956
Kernel command line: console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rootwait splash
Trying to install chained interrupt handler for IRQ0
Trying to install chained interrupt handler for IRQ1
Trying to install chained interrupt handler for IRQ32
Trying to install chained interrupt handler for IRQ33
PID hash table entries: 512 (order: 9, 2048 bytes)
timer tcon=00600000, tcnt 103c3, tcfg 00000400,00000000, usec 00001340
Console: colour dummy device 80x30
console [ttySAC0] enabled
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 114MB = 114MB total
Memory: 112768KB available (2136K code, 189K data, 492K init)
SLUB: Genslabs=11, HWalign=32, Order=0-1, MinObjects=4, CPUs=1, Nodes=1
Calibrating delay loop... 530.84 BogoMIPS (lpj=1327104)
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
net_namespace: 64 bytes
NET: Registered protocol family 16
S3C6410 Power Management, (c) 2008 Samsung Electronics
s3c6410: Initialising architecture
S3C DMA-pl080 Controller Driver, (c) 2006-2007 Samsung Electronics
Total 32 DMA channels will be initialized.
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP reno registered
S3C PWM Driver, (c) 2006-2007 Samsung Electronics
io scheduler noop registered
io scheduler cfq registered (default)
S3C_LCD clock got enabled :: 133.000 Mhz
LCD TYPE :: TD043MTEX will be initialized
Window[0] - FB1: map_video_memory: clear ff200000:000bb800
            FB1: map_video_memory: dma=56900000 cpu=ff200000 size=000bb800
fb0: s3cfb frame buffer device
LCD TYPE :: TD043MTEX will be initialized
s3c-uart.0: s3c_serial0 at MMIO 0x7f005000 (irq = 37) is a S3C
s3c-uart.1: s3c_serial1 at MMIO 0x7f005400 (irq = 38) is a S3C
s3c-uart.2: s3c_serial2 at MMIO 0x7f005800 (irq = 39) is a S3C
s3c-uart.3: s3c_serial3 at MMIO 0x7f005c00 (irq = 40) is a S3C
RAMDISK driver initialized: 2 RAM disks of 8192K size 1024 blocksize
usbmon: debugfs is not available
Loaded s3c-udc version Apr  9 2009 (DMA Mode)
S3C Touchscreen driver, (c) 2008 Samsung Electronics
S3C TouchScreen got loaded successfully : 12 bits
input: S3C TouchScreen as /devices/virtual/input/input0
S3C24XX RTC, (c) 2004,2006 Simtec Electronics
s3c2410-rtc s3c2410-rtc: rtc disabled, re-enabling
s3c2410-rtc s3c2410-rtc: rtc core: registered s3c as rtc0
s3c64xx-i2c s3c64xx-i2c.0: slave address 0x10
s3c64xx-i2c s3c64xx-i2c.0: bus frequency set to 377 KHz
s3c64xx-i2c s3c64xx-i2c.0: i2c-0: S3C64XX I2C adapter
s3c64xx-i2c s3c64xx-i2c.1: slave address 0x10
s3c64xx-i2c s3c64xx-i2c.1: bus frequency set to 377 KHz
s3c64xx-i2c s3c64xx-i2c.1: i2c-1: S3C64XX I2C adapter
S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics
s3c2410-wdt s3c2410-wdt: watchdog inactive, reset disabled, irq enabled
Advanced Linux Sound Architecture Driver Version 1.0.15 (Tue Nov 20 19:16:42 2007 UTC).
ASoC version 0.13.1
WM8987: Audio Codec Driver v0.12
asoc: WM8987 <-> s3c-i2s mapping ok
Proc-FS interface for audio codec
ALSA device list:
  #0: smdk6400 (WM8987)
TCP cubic registered
NET: Registered protocol family 1
VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 5
input: gpio-keys as /devices/platform/gpio-keys.0/input/input1
input: gpio-keys as /devices/platform/gpio-keys.1/input/input2
s3c2410-rtc s3c2410-rtc: setting system clock to 2009-05-04 17:40:17 UTC (1241458817)
[s3c_hsmmc_probe]: s3c-hsmmc.1: at 0xc7c00000 with irq 57. clk src: sclk_DOUTmpll_mmc1
s3c-hsmmc: card inserted.
[s3c_hsmmc_probe]: s3c-hsmmc.0: at 0xc7e00000 with irq 56. clk src: sclk_DOUTmpll_mmc0
[s3c_hsmmc_probe]: s3c-hsmmc.2: at 0xc8000000 with irq 49. clk src: sclk_DOUTmpll_mmc2
Waiting for root device /dev/mmcblk0p1...
mmc0: host does not support reading read-only switch. assuming write-enable.
mmc0: new high speed SD card at address d555
mmcblk0: mmc0:d555 ST01G 1003264KiB 
 mmcblk0: p1 p2 p3
mmc2: new SDIO card at address 0001
kjournald starting.  Commit interval 5 seconds
EXT3 FS on mmcblk0p1, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
VFS: Mounted root (ext3 filesystem).
Freeing init memory: 492K
UART err int.
mmc1: host does not support reading read-only switch. assuming write-enable.
mmc1: new high speed SDHC card at address 0002
mmcblk1: mmc1:0002 SD4GB 3948544KiB 
 mmcblk1: p1 p2 p3
g_file_storage gadget: File-backed Storage Gadget, version: 7 August 2007
g_file_storage gadget: Number of LUNs=1
g_file_storage gadget-lun0: ro=0, file: /dev/mmcblk1p1
Registered gadget driver 'g_file_storage'
8686 sdio: sd 8686 driver
8686 sdio: Copyright HHCN 2009
Adding 125992k swap on /dev/mmcblk0p3.  Priority:-1 extents:1 across:125992k
EXT3 FS on mmcblk0p1, internal journal
kjournald starting.  Commit interval 5 seconds
EXT3 FS on mmcblk0p2, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
Bluetooth: Core ver 2.11
NET: Registered protocol family 31
Bluetooth: HCI device and connection manager initialized
Bluetooth: HCI socket layer initialized
Bluetooth: L2CAP ver 2.9
Bluetooth: L2CAP socket layer initialized
Bluetooth: RFCOMM socket layer initialized
Bluetooth: RFCOMM TTY layer initialized
Bluetooth: RFCOMM ver 1.8
Bluetooth: SCO (Voice Link) ver 0.5
Bluetooth: SCO socket layer initialized
Bluetooth: BNEP (Ethernet Emulation) ver 1.2
Bluetooth: BNEP filters: protocol multicast
S3C6400 MFC Driver, (c) 2007 Samsung Electronics
S3C6400 MFC driver module init OK.
S3C PostProcessor Driver v3.10, (c) 2008 Samsung Electronics
LCD TYPE :: TD043MTEX will be initialized
LCD TYPE :: TD043MTEX will be initialized
kjournald starting.  Commit interval 5 seconds
EXT3 FS on mmcblk1p3, internal journal
EXT3-fs: mounted filesystem with ordered data mode.
Unregistered gadget driver 'g_file_storage'
ether gadget: using random self ethernet address
ether gadget: using random host ethernet address
usb0: Ethernet Gadget, version: May Day 2005
usb0: using s3c-udc, OUT ep1-bulk IN ep2-bulk STATUS ep3-int
usb0: MAC 3e:aa:ad:4c:0d:43
usb0: HOST MAC ca:98:c6:aa:b1:66
usb0: RNDIS ready
Registered gadget driver 'ether'
usb0: high speed config #1: 100 mA, Ethernet Gadget, using CDC Ethernet
LCD TYPE :: TD043MTEX will be initialized

1 Photos
2 Boot process
3 Firmware image format
4 Hardware support

[edit] Photos

SmartQ 5 MID with its preinstalled chinese OS

Circuit board

Circuit board with battery attached

[edit] Boot process

Block size = 512 byte

Upon booting, IROM will decide wether to boot internal SD or external SD, based on if the second button from right is held down. If held down, it will boot from external SD.

On a SDHC card, it will boot from 1042 blocks before the end of the card (16 + 1 + 1025), On a SD card this will be on 18 blocks before the end of the card (16 + 1 + 1).

This is where qi is placed, maximum 16 blocks size, zero out the remaining 2/1027 blocks

Qi will then (see /qi/src/cpu/s3c6410/start_qi.c) try to locate a SmartQ firmware image (see genimage for format, or same file, struct FirmHead on 32768 blocks before the end, or 16384 blocks before the end, and load u-boot from the firmware image.

If this fails it will load u-boot from 512+18 blocks before the end, maximum size 512 blocks.

Then, in u-boot (see u-boot/board/samsung/smdk6410/cmd_hhtech.c), it will check first if battery is low and blink LEDS (red) and power off if so (see init_hard_last)

It will then, if a key is pressed:

KEY_UP (+ optional key power): load firmware file from SD, booting kernel + initramfs from it

KEY_LEFT (+ optional key power): load initramfs + kernel from iNAND in similar manner as Qi with FirmHead on 16384.. -- there's no left button on a SmartQ5

KEY_FACTORY (key down + key power): add factory to boot statement

or:

load kernel from iNAND in similar manner as Qi with FirmHead on 16384/32768

if fail, load initramfs image from SD

[edit] Firmware image format

typedef struct _firmware_fileheader {
    uint32_t magic;        // '2\0\09'= 0x32 0x00 0x00 0x39
    uint32_t check_sum; // for 8 ~ .fh_size 
    uint32_t fh_size;
    uint32_t version;      // major.minor.revision.xxx, each section in 8-bits
    uint32_t date;          // seconds since the Epoch
    char vendor[32];       // XXX: uint32_t vendor_string_len; char vendor_string[] 
    //uint32_t nand_off_end1=16M/512, nand_off_end2=8M/512;  // offset from INAND END(BLOCKS)
    uint32_t component_count /* = 5*/;
    struct {
        struct {
            uint32_t offset, size; /* nand offset in blocks, sizes and file offset in bytes */ 
        } file, nand;
        uint32_t check_sum;
    }qi, u_boot, zimage, initramfs, rootfs; // components[];
}FirmHead;

Offset in NAND is meant as offset from 16/8mb end offset in blocks (512 byte blocks). If offset is 0, it is not meant to be in the NAND image (qi doesn't make any sense there, nor rootfs, etc)

[edit] Hardware support

Power management
- Bluetooth
- USB otg / Host
- WiFi (on/off, PSM)
- Backlight control + dimming/turn off
SD slot automounting
Open source upgrade tool and initramfs
Updated u-boot
Audio: Headphone / loudspeaker switch
TV out
Microphone?
Hardware buttons support
XAA

Retrieved from "https://wiki.maemo.org/Mer/Status/SmartQ5"

Categories: Mer | Out of date

This page was last modified on 22 September 2010, at 10:56.
This page has been accessed 23,938 times.

Personal tools

Navigation

Views

Mer/Status/SmartQ5

Contents

[edit] Photos

[edit] Boot process

[edit] Firmware image format

[edit] Hardware support